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Introduction to Computer Architecture Lab

CSE-141L, Summer Session I 2021

The course offers hands-on computer architecture project aiming to familiarize students with instruction set architecture, design of processor, and control and memory systems, and I/O systems. This is a computer architecture project course. Together, we design a complete special-purpose processor from grounds up. I hope that you will have fun taking this course as much as we will enjoy teaching it!

This course is designed to run alongside CSE 141. We expect that you are enrolled in both.


Teaching Assistants

Yajie Sun she/her

Link Lin he/him


Lectures are Monday from 2:00 to 3:50 US/Pacific, on Zoom.

Labs are Wednesday from 2:00 to 3:50 US/Pacific, on Zoom.

Updated Office Hours on Canvas (See Course Calendar).


CSE 110, CSE 140, and CSE 140L. CSE 141 should be taken either before or concurrently.


There is no textbook for the class, but you will find the CSE 141 textbook helpful in many ways during the lab: Computer Organization and Design MIPS Edition, The Hardware/Software Interface, Fifth Edition (Patterson & Hennessy) (ISBN-13: 978-0124077263, ISBN-10: 0124077269)


Course format is lectures over Zoom, two days per week, plus independent work over CloudLabs or self-contained at home on own computers. Attendance is strongly recommended, but not required, and all lectures are recorded.

Online Discussion

Discussions, Q&A, peer-to-peer instruction, etc. take place on our edstem. You should have received an invitiation email to join the course. Please contact Kazem if you have not. You are encouraged to post questions, help answer other students’ questions, and provide feedback and suggestions to your instruction staff. Constructive criticism is always welcome.

While the instruction staff will do their best to answer any question as soon as possible, be aware (and plan ahead) that instruction staff will not be available 24/7.


Students shall work in teams of two to four members each. There are four lab reports, due at the starts of the 3rd, 4th, 5th weeks and the end (Sunday night) of the 5th week. See Canvas for specifics. Reports shall be submitted on Gradescope (the canvas page needs Chrome or Firefox).


Each team shall design a microprocessor – its ISA, its hardware, and its software (assembly code). These will be tested on three program assignments, and final course grades will depend mostly on Lab 4. The first three labs each constitude 5% of your final grade. The remaining 85% depends on Lab 4. Lab 4 will be graded on the number of programs your processor can run:

  • Only one program runs properly -> 80% of Lab 4’s grade
  • Two programs run properly -> 90% of Lab 4’s grade
  • Three programs run properly -> 100% of Lab 4’s grade

We will use the following scale for your final grade:


We reserve the right to modify these ranges, however, we will only modify them in your favor.

Academic Integrity

This is a collaborative course, but students are expected to do their own work and to refrain from taking credit for the work of others. Cheating WILL be taken seriously. It is not fair to honest students to take cheating lightly, nor is it fair to the cheater to let him/her go on thinking that is a reasonable alternative in life.

“Don’t test me on this one.” ~Prof. Dean Tullsen

The following is not considered cheating:

  • discussing the tools or logic design techniques with other groups.

The following is:

  • Copying lab designs from someone who is not your partner, or lab report text from anyone.
  • Viewing lab designs or lab reports from anyone who is not your partner, including those who have taken the class in previous years.
  • Altering timing data produced by simulation, e.g. to make a non-working design appear to be working.

Penalties – anyone copying information or having information copied on a lab, or any other violation of class policy, will receive an F in the class and will not be allowed to drop. They will be reported to their college dean. If you can prove non-cooperative copying took place, your grade may be restored, but you must prove it to the dean – I don’t want to be involved.

Late Assignments

No late turn-ins for any Lab. Sunday night at the end of Week 5 is an absolute cutoff for Lab 4.

Useful Resources



Jun 28
Juneteenth Holiday (Observed)
Jun 30
LabIntroduction, ISAs
Lab 1 release


Jul 05
Independence Day (Observed)
Jul 05
Async VideoDesigning an Example ISA
Jul 07
LabLab1 Q/A



Jul 19
SectionLab 3 and 4
Lab 3,4 release
Jul 20
Lab 2 due
Jul 21
Lab Debugging


Jul 26
SectionProject Q/A
Lab 3 due
Jul 28
Lab Project Q/A
Aug 1
Strict Deadline for Lab 4
Lab 4 due


Due to our unusual circumstances, the details in this syllabus may change (e.g. schedule, grading policy, assignments, etc.). We will update this syllabus in the event of changes as the course progresses.


This page uses materials from John Eldon and Dean Tullsen.